In the course of Integrated Circuit (IC) development, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. At the same time, the scaling down process also increases the significance of process-induced inconsistency of the components, between their actual sizes and shapes as manufactured in a real IC and those as designed in an Electronic Design Automation (EAD) tool.